1. Field of the Invention
The present invention relates to a method of manufacturing a substrate including a laminating step of obtaining a multilayer substrate having an insulation layer and a conductive pattern laminated alternately, and a processing step of processing the substrate obtained at the laminating step, and a circuit board.
2. Description of the Related Art
As a representative method of manufacturing a multilayer substrate, what is called a buildup method is known for alternately laminating an insulation layer and a wiring such as a power source line and a ground line or a conductive pattern as a pad, on a core board (refer to Japanese Patent Application Publication No. 5-335744 and Japanese Patent Application Publication No. 10-341081, for example). Particularly, according to the buildup methods described in the Japanese Patent Application Publication No. 5-335744 and Japanese Patent Application Publication No. 10-341081, in order to increase the degree of adhesion between the insulation layer and the conductive pattern, the whole surface of the insulation layer is roughened, and the conductive pattern is formed on this rough surface of the insulation layer.
When an LSI (large scale integration) chip is mounted on the obtained multilayer substrate, a noise reduction element to reduce noise between the power source line and the ground line is also mounted in some cases. To increase a noise reduction rate according to the noise reduction element, the noise reduction element should be mounted on the substrate as close to the LSI chip as possible. For this purpose, a technique of embedding chip capacitors into the core board is proposed (refer to NE/NμD Hardware Conference 2002 (held by Nikkei Electronics and Nikkei Micro Device) draft paper, “The trend and technical development of a high-density multilayer resin substrate package”, Nobukazu Wakabayashi, May 30, 2002, pp. 3-16, for example).
FIG. 19 is a schematic diagram of a circuit board having chip capacitors embedded into the core board by applying the technique described in the above literature at the NE/NμD Hardware Conference 2002.
FIG. 19 shows a state that a circuit board 1′ is mounted on a mother board 9′. FIG. 19 also shows a core board 3′, and buildup layers 4′ provided on both the upper surface and the lower surface of the core board 3′, to constitute the circuit board 1′. An LSI chip 2′ is mounted on the surface of the circuit board 1′ shown in FIG. 19. Chip capacitors 5′ embedded in the core board 3′ are connected to the LSI chip 2′ through via holes 6′.
To manufacture the circuit board 1′ shown in FIG. 19, a groove 3′a is first formed on the surface of the core board, and the chip capacitors 5′ are put into the groove 3′a. The chip capacitors 5′ are fixed to the groove 3′a with an adhesive or the like. A resin is poured into the groove 3′a to fill the groove 3′a with the resin. The buildup layer 4′ is formed on the surface of the core board. The via holes 6′ are formed in the buildup layer 4′ to electrically connect the LSI chip 2′ with the chip capacitors 5′.
However, in order to embed the chip capacitors 5′ into the core board 3′, the upper surface of the chip capacitors 5′ and the upper surface of the core board 3′ need to be at the same level. Therefore, a high-precision processing technique is necessary to form the groove 3′a on the core board 3′. Positioning in the lateral direction of the chip capacitors 5′ also requires high precision. When a void is created in the resin that is poured into the grooves 3′a, air in the void is heated and blows out at the subsequent soldering, which has a risk of internal breakage of the circuit board. When the surface of the resin filled in the groove 3′a cannot secure sufficient flatness, the buildup layer 4′ swells, creating a risk of poor yield in the connection of fine LSI bumps.